A well known technique for debugging the operation of data processor based systems is tracing the instructions executed by the data processor during a specified time interval or until a specified hardware or software breakpoint occurs. It is advantageous to trace only those instructions which are actually executed during the trace period. However, this can be difficult in data processors which utilize pipelined architectures. More specifically, when a branch instruction is encountered in a pipelined architecture, the processor must generally handle a number of intervening instructions before the branch can actually be taken. The number of intervening instructions is a function of the pipeline length, the longer the pipeline the more intervening instructions. Each intervening instruction is said to occupy a delay slot in the execution of the branch instruction, because the processing of each intervening instruction represents a delay in the ultimate execution of the branch instruction.
In many pipelined architectures, the branch instruction opcode itself has a bit set aside to annul execution of the intervening instructions. In addition, some emulation features may cause execution to be halted. In both instances, the processor may fetch instructions which are never executed. Therefore, if it is desired to trace only those instructions which are actually executed, then the aforementioned instructions which are fetched but never executed should not be traced.
It is therefore desirable to provide a pipelined data processing device which is capable of selectively tracing only those instructions which are actually executed.
It is further desirable to reduce the number of executed instructions which are actually traced in order to reduce the amount of hardware needed for storage of the traced instructions.
As discussed above, when a branch instruction is introduced into a data processor having a pipelined architecture, before the branch can be taken the processor must generally handle one or more intervening instructions during one or more delay slots. If processor execution is stopped (e.g. emulation halt, interrupt) during a delay slot, the branch instruction is lost before the branch is taken. For this reason, pipelined architectures generally prohibit interrupts, traps etc. during delay slots of branch instructions, which disadvantageously complicates programming rules and processor design.
It is therefore desirable to provide a pipelined data processor which can be stopped during a delay slot of a branch instruction without losing the branch information. According to the present invention, an address pipeline is provided to hold the addresses of the instructions presently in the instruction pipeline. The address pipeline facilitates tracing only executed instructions, and permits stopping the data processor during a branch delay slot without losing the branch information.